CMOS

“What we didn’t realize was that it would reduce the cost of electronic functions by a factor of a million to one” - Jack Kilby

Complementary Metal-Oxide-Semiconductors

What is CMOS?

CMOS stands for Complementary Metal–Oxide–Semiconductor.

MOSFET Structure and Terminals

The MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is the building block of CMOS. It has four key regions:

Source: where carriers (electrons) enter the channel.

Drain : where carriers exit.

Gate : a metal electrode.It acts as a literal gate.
The Voltage applied determine the amount of conduction

Substrate: the silicon base material where the channel is formed. Sometimes tied to ground or VDD.

When the gate voltage exceeds a threshold, it creates an inversion layer (a channel) that lets current flow from source to drain.

What is a Hole?

A Hole, represents a vacancy of electron.

They acts as a mobile positive charge.

Valence Electrons in Silicon:

In (Si), there are 4 valence electrons. Yet, they are poor conductors under room temperature.

Making pMOS:

To improve conductivity:
BORON is added

Why Boron:

  • If we add boron (B), which has 3 valence electrons:

  • It bonds with 3 of silicon’s neighbors, but one bond is incomplete.

This missing electron spot is called a hole.

Since the boron atom still has one more proton than electrons, the hole behaves like a positive charge site.

How to MOVE HOLES:

Holes are not real. They are an absence of electrons.

If an electron jump from one atom to another. It fill a hole but also creates a new one.
To the external observer, it felt as if the empty seat had move

NMOS with Resistor Load (Before CMOS)

The Pipe is always leaking water…

Before CMOS became the mainstream, the dominant technologies were TTL and NMOS logic circuits.

In an NMOS logic circuit, only the nMOS “guard” is on duty. To make it work properly, it also requires a resistor.

The resistor is like a pipe that constantly leaks water. Even if the guard shuts the gate, water (current) still keeps dripping through - causing power waste.

So although NMOS circuits could function, they consumed too much power and were not suitable for large-scale integration.

Complementary of nMOS and pMOS

So what does complementary really mean? It refers to the complement of 1 and 0.

In CMOS, there are two “security guards”:

The nMOS guard: If you give him an “open” signal (a HIGH voltage), he obediently opens the gate and lets current pass. If there’s no signal, he closes the gate. Very well-behaved.

The pMOS guard: His temperament is the opposite. If you give him the “open” signal, he refuses and slams the gate shut. But if you don’t give him the signal, he actually opens the gate and connects the output to the power supply.

When you pair these two opposite-tempered guards together:

  • If the input is 0, the pMOS opens the gate and connects the output to VDD, while the nMOS stays shut.
  • If the input is 1, the nMOS opens the gate and connects the output to GND, while the pMOS shuts the gate.

This way, unlike the old NMOS circuits that always leaked current, CMOS outputs are stable and energy-efficient.

Why can’t both of them be open at the same time?

If both gates are open, the water will simple flow from VDD and GND, wasting energy.

Analog vs Digital

Analog: continuous signals, can take any value. Varies continuously.

Digital: only two states (0 or 1), like a switch ON or OFF. Example: logic gates in CPUs.

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E.g.
Real world (sound, temperature, light...) is analog.
Computer processors are digital.

To connect them:

ADC (Analog-to-Digital Converter): converts microphone voltages into binary numbers for your device.

DAC (Digital-to-Analog Converter): converts MP3 file bits into smooth voltages that drive your headphones.

Why did designers choose digital over analog?

First, NOISE IMMUNITY:

Digital circuits are not emotionally sensitive: they are black or white

Digital circuits only use two discrete levels: 0 or 1 with wide noise margins.

  • On the other hand, analog are very sensitive. +/- 0.1 Volt can make a difference.

Second, Scalability

  • Digital circuits are small and easy to integrate.

Third, Flexibility

  • The 0s and 1s can be stored, copied, transmitted without any degradation.

Fourth, Low Power

  • In analog, transistors often operate in linear mode (always conducting some current).

In CMOS digital logic, transistors only consume significant current when switching. Where pMOS and cMOS are on at the same time. At rest, almost zero static power.

SOI (Silicon-On-Insulator)

SOI is a special CMOS technology:

  • Instead of building MOSFETs directly on bulk silicon, they are built on a thin silicon layer above an insulating oxide layer.

Advantages:

Reduces Parasitic Capacitance

  • High operating Speed

What is Parasitic Capacitance?

Parasitic Capacitance,Cross talks, Bandwidth Effect, Miller Effects are difficult. I added a link.

Concept What It Means / Why It Matters
Parasitic Capacitance Unintended capacitance between nearby conductors—can distort signals.
Crosstalk When a signal unintentionally transfers energy to another line.
Bandwidth Effects Adds unwanted filtering, limiting signal speeds.
Miller Effect Amplifies gate-to-drain capacitance, harmful to amplifier speed.
Every Component Has Parasitics PCBs, transistors, inductors—all contribute.

Lowers leakage:

  • Save energy

Better isolation between devices:

  • Less noise

BUT, more expensive manufacturing.

Thus, bulk CMOS is cheaper for mass production, while SOI CMOS is used in high-performance or low-power niches.

Key RF Parameters in CMOS

Psat (Saturated Output Power): max RF output before distortion.

PAE (Power-Added Efficiency): efficiency of converting DC power to RF.
The power-added efficiency (PAE) is a standard figure of merit for RF power amplifiers.

The formula is:

PAE=Pout−PinPDC×100%\text{PAE} = \frac{P_{out} - P_{in}}{P_{DC}} \times 100\%

  • PoutP_{out} = RF output power (linear power, not in dBm)
  • PinP_{in} = RF input power
  • PDCP_{DC} = DC power consumed by the amplifier = VDD×IDDV_{DD} \times I_{DD}

Noise Figure: how much noise the receiver adds.

Scanning Angle: how wide a phased-array antenna beam can steer.

These parameters determine if a CMOS RF chip is practical for radar, satellite, or 5G use.

Why does frequency makes a difference?

You don’t need AI to open a door. You can’t use a marathon shoe to run a 100 m sprint.
KHz, MHz, GHz, THz

Find the right frequency for the right case.

ADV of LOW FREQUENCY

  • Saves Power.

  • Don’t need high-end chips.

  • Cheaper and more stable.

Roles:

Control logic (turning TR modules on/off, biasing).

Signal processing at baseband (after RF is downconverted).

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What is BASEHAND and DOWNCONVERTED?

Baseband = the original, (0- few MHz) signal before it is shifted (“modulated”) to a higher frequency for transmission.

E.g.:
When you talk: your voice is analog, between 0–4 kHz. That’s the baseband signal.

The phone can’t just send 0–4 kHz directly over the air — antennas need much higher frequencies.

So the baseband is modulated onto a carrier, e.g., 2.4 GHz for Wi-Fi or 28 GHz for 5G.

At the receiver, the RF is downconverted back to baseband for processing.

Analog accuracy (ADCs, DACs, op-amps).

Modern Case:

A company developed CMOS-based TR chips for phased-array antennas. They claim to be 50% the price of GaAS based TR chips.

What is TR?
(Transmit and receive)
Each chip integrates:

  • Tx/Rx amplifiers
    • Boost the weak RF signal during Transmit/Recieve phase
  • Phase shifters
    • Alters the angle of an RF signal without changing the amplitude
  • Control circuits

    • control circuits use low-power signals to control actions like activation, deactivation, and interlocking

    • In a phased the control circuits interpret commands to determine the desired beam direction. They then calculate and send the specific digital or analog control signals needed to set the correct phase shift for each element’s phase shifter.

There are a lot more to learn. And here is a link for you.

What is an RF Phase Shifter?

Their CMOS chip achieved:

  • Psat ≈ 12.5 dBm (output power per element)
  • PAE > 12% (power efficiency)
  • Noise Figure ≈ 9 dB
  • Scanning angle ≈ ±45°

The single array of CMOS cost:

200 RMB compared to 20000
20mW compared to 4-5W

How CMOS Competes with GaAs

GaAs TR modules (Market RN):

Module Type / Frequency Range PSAT (dBm) Noise Figure (dB) PAE (%)
Mid-power MMIC (ADL8150, 6–14 GHz) ~23 dBm ~3.5 dB ~10–20 %
Higher-freq MMIC (ADL9006, 14–22 GHz) ~15–18 dBm 2.2–4 dB NA

  • BUT:

    • Very expensive to manufacture.
    • Difficult to integrate digital control (needs separate chips).
    • Not scalable to thousands of channels for low-cost systems.

GaAs = raw RF performance, higher power, lower noise.

CMOS = integration, scalability, low cost, and now “good enough” RF performance.

Why CMOS is the trend?

Even though each CMOS element is weaker, in a large phased array, _the scale overcomes the ‘scope’.
Cost per channel is dramatically lower. This allows mass deployment (5G base stations, automotive radar, satellite internet).